1. Field of the Invention
This invention relates to a semiconductor device manufacturing method and a semiconductor device.
2. Background Art
A technique for three-dimensionally arranging memory cells is proposed in, for instance, JP-A 2007-180389 (Kokai). In this technique, a plurality of electrode layers functioning as control gates in a memory device are stacked alternately with insulating layers to form a multilayer body, in which silicon pillars are provided via a charge storage layer.
JP-A 2007-180389 (Kokai) also discloses a staircase structure of electrode layers as a structure for connecting each of a plurality of stacked electrode layers to an upper interconnect. In other words, toward the bottom, each of the electrode layers is made longer. Furthermore, a contact hole reaching each of the electrode layers is formed in an interlayer insulating layer covering the staircase structure, and a contact electrode is buried in the contact hole.
JP-A 2007-180389 (Kokai) further discloses forming a trench in a multilayer body of a memory cell array region to expose the side surface of each of the electrode layers into the trench, forming a metal film in the trench, and then performing annealing to turn the side surface of each of the electrode layers made of silicon into metal silicide. It is desired to turn also the electrode layers of the staircase-shaped contact portion into metal silicide to reduce resistance. However, the staircase-shaped contact portion is different from the memory cell array in its structure and formation process. Thus, the metal silicidation process for the memory cell array cannot be directly applied thereto.